Memory elements using self-aligned phase change material layers and methods of manufacturing same

ABSTRACT

A memory element and method of forming the same. The memory element includes a substrate supporting a first electrode, a dielectric layer over the first electrode having a via exposing a portion of the first electrode, a phase change material layer formed over sidewalls of the via and contacting the exposed portion of the first electrode, insulating material formed over the phase change material layer and a second electrode formed over the insulating material and contacting the phase change material layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/400,044, filed Mar. 9, 2009, now allowed, which is a continuation ofU.S. application Ser. No. 11/396,616, filed Apr. 4, 2006, now U.S. Pat.No. 7,812,334, the entirety of which are both incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices, and inparticular to phase change memory elements and methods of forming andusing the same.

BACKGROUND OF THE INVENTION

Non-volatile memories are important elements of integrated circuits dueto their ability to maintain data absent a power supply. Phase changematerials have been investigated for use in non-volatile memory cells.Phase change memory elements include phase change materials, such aschalcogenide alloys, which are capable of stably transitioning betweenamorphous and crystalline phases. Each phase exhibits a particularresistance state and the resistance states distinguish the logic valuesof the memory element. Specifically, an amorphous state exhibits arelatively high resistance, and a crystalline state exhibits arelatively low resistance.

A conventional phase change memory element 1, illustrated in FIGS. 1Aand 1B, has a layer of phase change material 8 between first and secondelectrodes 2, 4, which are supported by a dielectric material 6. Thephase change material 8 is set to a particular resistance stateaccording to the amount of current applied by the first and secondelectrodes 2, 4. To obtain an amorphous state (FIG. 1B), a relativelyhigh write current pulse (a reset pulse) is applied through theconventional phase change memory element 1 to melt at least a portion ofthe phase change material 8 covering the first electrode 2 for a firstperiod of time. The current is removed and the phase change material 8cools rapidly to a temperature below the crystallization temperature,which results in the portion of the phase change material 8 covering thefirst electrode 2 having the amorphous phase. To obtain a crystallinestate (FIG. 1A), a lower current write pulse (a set pulse) is applied tothe conventional phase change memory element 1 for a second period oftime (typically longer in duration than the first period of time andcrystallization time of amorphous phase change material) to heat theamorphous portion of the phase change material 8 to a temperature belowits melting point, but above its crystallization temperature. Thiscauses the amorphous portion of the phase change material 8 tore-crystallize to the crystalline phase that is maintained once thecurrent is removed and the conventional phase change memory element 1 iscooled. The phase change memory element 1 is read by applying a readvoltage which does not change the phase state of the phase changematerial 8.

A sought after characteristic of non-volatile memory is low powerconsumption. Often, however, conventional phase change memory elementsrequire large operating currents. It is therefore desirable to providephase change memory elements with reduced current requirements. Forphase change memory elements, it is necessary to have a current densitythat will heat the phase change material past its melting point andquench it in an amorphous state. One way to increase current density isto decrease the size of a first electrode. These methods maximize thecurrent density at the first electrode interface to the phase changematerial. Although these conventional solutions are typicallysuccessful, it is desirable to further reduce the overall current in thephase change memory element, thereby reducing power consumption incertain applications.

Another desired property of phase change memory is its switchingreliability and consistency. Conventional phase change memory elements(e.g., phase change memory element 1 of FIGS. 1A and 1B) haveprogrammable regions of the phase change material layer that are notconfined, and have the freedom to extend sideways and the interfacebetween the amorphous portions and crystalline portions of the phasechange material may cause reliability issues. The proposed inventionsconfines the cell so that it reduces the ability to have sidewayextension during the change from crystalline to amorphous phases orinadvertent failure.

BRIEF SUMMARY OF THE INVENTION

Exemplary embodiments of the invention provide phase change memoryelements and methods of forming the same. An exemplary memory elementincludes a substrate supporting a first electrode. An insulatingmaterial element is positioned over the first electrode, and a phasechange material layer is formed over the first electrode and surroundingthe insulating material element such that the phase change materiallayer has a lower surface that is in electrical communication with thefirst electrode. The memory element also has a second electrode inelectrical communication with an upper surface of the phase changematerial layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages and features of the invention willbecome more apparent from the detailed description of exemplaryembodiments provided below with reference to the accompanying drawingsin which:

FIGS. 1A-1B illustrate a conventional phase change memory element;

FIGS. 2A-2B illustrate partial cross-sectional and partial top-downviews, respectively, of a phase change memory element constructed inaccordance with an exemplary embodiment of the invention;

FIGS. 3A-5B illustrate partial cross-sectional and partial top-downviews of an exemplary method of fabricating the phase change memoryelement of FIGS. 2A and 2B;

FIGS. 6A-6B illustrate partial cross-sectional and partial top-downviews, respectively, of a phase change memory element constructed inaccordance with a second exemplary embodiment of the invention;

FIGS. 7A-8B illustrate partial cross-sectional and partial top-downviews of an exemplary method of fabricating the phase change memoryelement of FIGS. 6A and 6B;

FIGS. 9A-9B illustrate partial cross-sectional and partial top-downviews, respectively, of an array phase change memory elementsconstructed in accordance with a third exemplary embodiment of theinvention;

FIGS. 10A-10B illustrate partial cross-sectional and partial top-downviews, respectively, of an array phase change memory elementsconstructed in accordance with a fourth exemplary embodiment of theinvention;

FIGS. 11A-11E illustrate partial cross-sectional and partial top-downviews of an array phase change memory elements constructed in accordancewith a fifth exemplary embodiment of the invention and an exemplarymethod of fabricating the fifth exemplary embodiment; and

FIG. 12 is a block diagram of a processor system having a memory deviceincorporating a phase change memory element constructed in accordancewith an exemplary embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to variousspecific embodiments of the invention. These embodiments are describedwith sufficient detail to enable those skilled in the art to practicethe invention. It is to be understood that other embodiments may beemployed, and that various structural, logical and electrical changesmay be made without departing from the spirit or scope of the invention.

The term “substrate” used in the following description may include anysupporting structure including, but not limited to, a semiconductorsubstrate that has an exposed substrate surface. A semiconductorsubstrate should be understood to include silicon, silicon-on-insulator(SOT), silicon-on-sapphire (SOS), doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures, including those made ofsemiconductors other than silicon. When reference is made to asemiconductor substrate or wafer in the following description, previousprocess steps may have been utilized to form regions or junctions in orover the base semiconductor or foundation. The substrate also need notbe semiconductor-based, but may be any support structure suitable forsupporting an integrated circuit, including, but not limited to, metals,alloys, glasses, polymers, ceramics, and any other supportive materialsas is known in the art.

The invention is now explained with reference to the figures, whichillustrate exemplary embodiments and throughout which like referencenumbers indicate like features. FIGS. 2A and 2B illustrate an exemplaryembodiment of a phase change memory element 100 constructed inaccordance with the invention.

The phase change memory element 100 includes a substrate 10 having afirst dielectric layer 12 formed thereon, and a first electrode 14formed in a via 24 within the first dielectric layer 12. The phasechange memory element 100 also includes a nitride element 16 formed overthe first electrode 14, and within a phase change material layer 18 thatsurrounds the nitride element 16. The phase change material layer 18 isitself surrounded by a second dielectric layer 20. The FIG. 2A phasechange memory element 100 also includes a second electrode 22 formedover the nitride element 16 and in electrical communication with thephase change material layer 18.

FIG. 2B illustrates a partial top-down view of the FIG. 2A phase changememory element 100. As illustrated, the phase change material layer 18surrounds the nitride element 16. The nitride element 16 and the phasechange material layer 18 are formed over the first electrode 14 suchthat the phase change material layer 18 is in electrical communicationwith the first electrode 14 (FIG. 2A). The first electrode 14 is formedwithin a via 24 of the first dielectric layer 12.

In operation, the FIG. 2A and 2B phase change memory element 100 has theadvantage of requiring less current (and, therefore, consumes lesspower) than typical phase change memory elements because of a reducedcontact area between the phase change material layer 18 and the firstelectrode 14 resulting in a reduced volume of programmable phase changematerial layer 18. The current necessary to change the phase of theprogrammable volume of the illustrated phase change material layer 18from crystalline to amorphous is decreased due to the decreased contactarea between the phase change material layer 18 and first and secondelectrodes 14, 22.

For example, conventional phase change memory elements (e.g.,conventional phase change memory element 1 of FIG. 1) typically have aphase change material layer with a programmable volume having, adiameter of about 75 nm and a height of about 50 nm resulting in avolume of about 2.2×10⁵ nm³. The current necessary to reset the phasechange material layer having a contact area of a diameter of about 75 nm(4.4×10³ nm²) and a volume of 2.2×10⁵ nm³ is approximately 2 mA.

By contrast, the phase change memory element 100 of FIGS. 2A and 2Bcould have a phase change material layer 18 with a programmable volumeof 5.9×10⁴ nm³ if the thickness t (FIG. 4A) of the phase change materiallayer 18 is about 5 nm and the height h (FIG. 4A) is the same as theprogrammable volume in the FIG. 1 phase change memory element 1. Thephase change memory element 100 of FIGS. 2A and 2B has a programmablevolume nearly one quarter the programmable volume of the conventionalphase change memory element. The contact area is also reduced to onequarter of the contact area that the conventional phase change materiallayers (e.g., phase change material layer 8 of FIGS. 1A and 1B) havewith first and second electrodes 2, 4 (FIGS. 1A and 1B). The reductionin the contact area and the programmable volume of the phase changematerial results in a reduction in the amount of current and powernecessary to reset the phase change material layer 18. For example, thecurrent necessary to reset the phase change material layer 18 having acontact area of 1.2×10³ nm² and volume of 5.9×10⁴ nm³ is approximately0.5 mA as compared to the 2 mA necessary to reset the phase changematerial of a conventional phase change memory element, and the powerconsumption is also reduced to one fourth of that of a conventionalphase change memory element.

The scaling of phase change memory elements indicates that the resetcurrent is approximately proportional to the area of contact between thephase change material and the first and second electrodes (e.g., firstand second electrodes 14, 22 of FIG. 2A). Accordingly, the phase changematerial layer 18 is deposited to surround a nitride element 16, therebyallowing the contact area of the phase change material layer 18 incontact with the first and second electrodes 14, 22 to be smaller thanif the nitride element 16 were not provided, and maintaining a reducedvolume of phase change material, while the contact area is linearlydependent on the phase change material layer 18 thickness, and can beprecisely controlled through the deposition of the phase changematerial.

FIGS. 3A-5B illustrate an exemplary method of fabricating the phasechange memory element 100 illustrated in FIGS. 2A and 2B. No particularorder is required for any of the actions described herein, except forthose logically requiring the results of prior actions. Accordingly,while the actions below are described as being performed in a specificorder, the order is exemplary only and can be altered if desired.Although the formation of a single phase change memory element 100 isshown, it should be appreciated that the phase change memory element 100can be one memory element in an array of memory elements, which can beformed concurrently.

FIGS. 3A and 3B illustrate a partial cross-sectional view and a partialtop-down view, respectively, of an intermediate structure 100 a. Theintermediate structure 100 a is formed by providing a first dielectriclayer 12 over a substrate 10. The first dielectric layer 12 is typicallyetched to create vias 24 (FIG. 2B) within which a first electrode 14 isformed. The first electrode 14 can be formed of any suitable conductivematerial, such as titanium-nitride (TiN), titanium-aluminum-nitride(TiAlN), titanium-tungsten (TiW), platinum (Pt) or tungsten (W), amongothers.

A nitride element precursor layer is formed and etched to produce anitride element 16. The nitride element 16 could be patterned to have asubstantially disk-like top-down shape (see FIG. 3B) having slopedsidewall regions 16 b to improve the step coverage of the phase changematerial deposition, discussed below. Although element 16 is formed as anitride, it could be formed of other materials. For example, the element16 could be formed of any insulating material such as, but limited to,silicon nitrides; alumina oxides; oxides; high temperature polymers; lowdielectric materials; insulating glass; or insulating polymers.

It should be noted that the disk-like top-down shape of the nitrideelement 16 is not intended to be limiting in any way. For example, thenitride element 16 could have a triangular, circular, or rectangulartop-down shape, as discussed below with respect to FIG. 9. It shouldalso be noted that the sloped sidewalls 16 b are only optional, and thatthe sidewalls of the nitride element 16 could be vertical relative to atop surface of the first electrode 14, linear, non-linear, bowed, slopedsuch that a top surface of the nitride element 16 has a greater surfacearea than that of a bottom surface, or any other desired shape.

FIGS. 4A and 4B illustrate the deposition of a conformal or a partiallyconformal phase change material on the sidewalls 16 b (FIG. 3A) of thenitride element 16 to form the phase change material layer 18. Thedeposited phase change material could be a chalcogenide material, suchas, for example, germanium-antimony-tellurium or germanium-telluridelayer. Exemplary phase change materials may also include, for example,Ge_(x)Sb_(y)Te_(z) (e.g., Ge₂Sb₂Te₅), GaSb, Ge_(x)Te_(y), SbTe (e.g.,Sb₂Te₃), InSb, InSe, In_(x)Sb_(y)Te_(z), Sn_(x)Sb_(y)Te_(z),Ga_(x)Se_(y)Te_(z), InSbGe, AgInSbTe, GeSnSbTe, Te_(x)Ge_(y)Sb_(z)S_(k)and GeSbSeTe.

The phase change material layer 18 could have an outside diameter d(FIG. 4B) in the range of about 20 nm to about 200 nm, a height h (FIG.4A) in the range of about 25 nm to about 75 nm, and a cross-sectionalthickness t (FIG. 4A) in the range of about 25/ to about 200/. Theillustrated phase change material layer 18 has a diameter d of about 75nm, a height of about 50 nm, and a cross-sectional thickness t of about50/. The structure parameters are not limited to the above-describedvalues; for example, the parameters can be adjusted for the intendedapplication.

Although, the FIG. 4A phase change material layer 18 has a first surface18 a that is planar to a first surface 16 a of the nitride element 16,it is not intended to be limiting in any way. For example, the firstsurface 16 a of the nitride element 16 could be lower than the firstsurface 18 a of the phase change material layer 18, as discussed belowwith respect to FIG. 6A.

It should also be noted that the phase change material layer 18 need notcompletely surround the nitride element 16. For example, the phasechange material layer 18 could partially surround the nitride element 16to further reduce the volume of the phase change material layer 18,which may further reduce the current necessary to switch the state ofthe phase change material layer 18.

FIGS. 5A and 5B illustrate the deposition of the second dielectric layer20 over the entire structure illustrated in FIGS. 4A and 4B. The seconddielectric layer 20 is subsequently planarized to the level of the uppersurface 18 a of phase change material layer 18. The second electrode 22(FIGS. 2A and 2B) is subsequently formed over the phase change materiallayer 18 and nitride element 16 to form the phase change memory element100 (FIGS. 2A and 2B).

Although illustrated as forming a single phase change memory element, itshould be understood that the illustrations and descriptions are notintended to be limiting in any way. Those skilled in the art willrecognize that a plurality of phase change memory elements are typicallyfabricated on a single substrate simultaneously. A single substratecould contain thousands or millions of phase change memory elements.

The phase change material layer 18 is the active phase change materialwith a fixed programmable volume that can be set to a crystalline stateor reset to an amorphous state by passing a heating current. Sinceswitching the state of the phase change material layer 18 involves areduced volume of phase change material, the switching stability andconsistency as well as cycling lifetime can be improved as the phasestate mixing is reduced

The thickness of the phase change material layer 18 on the sidewall 16 b(FIG. 3A) of the nitride element 16 can be varied, depending on thedesired application, to greatly reduce the contact area between phasechange material layer 18 and the first and second electrodes 14, 22(FIGS. 2A and 2B), the programmable current cross-section area, and theprogrammable volume, thereby resulting in the reduction of theprogramming current requirement.

It should be noted that although the thickness of the phase changematerial layer 18 on the sidewall 16 b (FIG. 3A) of the nitride element16 is illustrated as being uniform, it is not intended to be limiting inany way.

Another advantage of the phase change memory element 100 relates tomitigating heat loss. The majority of heat loss in conventional phasechange memory elements during the heating process is due to the heatconduction through the first and second electrodes, which have highthermal conductivity; by reducing the contact area between the phasechange material layer 18 and the first and second electrodes 14, 22, theamount of heat loss is mitigated to further reduce the programmingcurrent.

Yet another advantage of the phase change memory element 100 relates tothe self-alignment with which the phase change material layer 18 isdeposited. Because the nitride elements 16 are formed over the firstelectrode 14, the phase change material layer 18 is self-aligned overthe first electrode 14 when deposited. The self-alignment of the phasechange material layer 18 with the first electrode 14 ensures that thereis an electrical communication with both components. The self-alignmentof the phase change material layer 18 with the first electrode 14 maysimplify the processing and fabrication of the overall phase changememory element 100, and may also increase throughput.

FIGS. 6A and 6B illustrate a second exemplary embodiment of a phasechange memory element 200 constructed in accordance with the invention.Specifically, FIGS. 6A and 6B illustrate a partial cross-sectional viewand a partial top-down view, respectively, of a phase change memoryelement 200 having a phase change material layer 218 formed on sidewalls216 a, 222 a of a nitride element 216 and a second electrode 222,respectively. Although, the second electrode 222 has a first surface 222b that is planar to a first surface 218 b of the phase change materiallayer 218, it is not intended to be limiting in any way. For example,the second electrode 222 could have a first surface 222 b that is loweror higher than that of the first surface 218 b of the phase changematerial layer 218. The phase change material layer 218 is self-alignedover the sidewalls 216 a, 222 a of the nitride element 216 and thesecond electrode 222, respectively.

The phase change memory element 200 also includes a first dielectriclayer 212 formed over a substrate 210, and has a first electrode 214formed therein. A second dielectric layer 220 is formed over the firstdielectric layer 212 and portions of the first electrode 214.

FIGS. 7A-8B illustrate an exemplary method of fabricating the FIG. 6Aand 6B phase change memory element 200 illustrated in FIGS. 6A and 6B.The first dielectric layer 212 is formed over a substrate 210. The firstelectrode 214 is formed within the first dielectric layer 212. A nitrideelement 216 is formed between the first electrode 214 and the secondelectrode 222. As discussed above with respect to FIGS. 3A and 3B, thenitride element 216 could be formed to have a substantially disk-likeshape (from a top-down view (FIG. 7B)) having sloped sidewalls 216 a forbetter step coverage of the phase change material deposition. The secondelectrode 222 is formed over the nitride element 216. The secondelectrode 222 could also be formed to have a substantially disk-liketop-down shape (FIG. 7B) having sloped sidewalls for better stepcoverage of the phase change material deposition. The materials used toform the nitride element 216 and the second electrode 222 are similar tothose discussed above with respect to FIGS. 3A-5B. The nitride element216 and the second electrode 222 could be formed in situ with onepatterning step, although it is not intended to be limiting in any way.

FIGS. 8A and 8B illustrate the deposition of the phase change materiallayer 218 over the sidewalls 216 a, 222 a of the nitride element 216 andthe second electrode 222, respectively. The phase change material layer218 could be formed of any material discussed above with respect toFIGS. 4A and 4B. The phase change material layer 218 could be formed tohave the same dimensions discussed above with respect to FIGS. 4A and4B.

The second dielectric layer 220 (FIG. 6A) is subsequently deposited overthe first dielectric layer 212 and a portion of the first electrode 214.The phase change memory element 200 (FIG. 6A) has a substantially planarsurface, which may further reduce the overall size of the phase changememory element 200. The planar surface may also provide for betterhandling during subsequent processing steps, and add to the overallrobustness of the phase change memory element 200.

Although the nitride element 216 is illustrated as having first surface216 b having a longer length l than a second surface 216 c of thenitride element 216 having a shorter length l′, it is not intended to belimiting in any way. For example, the second surface 216 c of thenitride element 216 could have a length l′ that is equal to or greaterthan the length l of the first surface 216 b of the nitride element 216.Additionally, although the sidewalls 216 a of the nitride element 216are illustrated as being substantially linear, it is not intended to belimiting in any way. For example, the sidewalls 216 a could benon-linear or have other desired shapes.

Similarly, although the length of a first surface 222 b of the secondelectrode 222 is illustrated as being longer than a length of a secondsurface 222 c, it is not intended to be limiting in any way. Forexample, the second surface 222 c of the second electrode 222 could havea length that is equal to or greater than the length of the firstsurface 222 b of the second electrode 222. Additionally, although thesidewalls 222 a of the second electrode 222 are illustrated as beingsubstantially linear, it is not intended to be limiting in any way. Forexample, the sidewalls 222 a could be non-linear or have other desiredshapes.

Although illustrated as forming a single phase change memory element200, it should be understood that the illustrations and descriptions arenot intended to be limiting in any way. Those skilled in the art willrecognize that a plurality of phase change memory elements are typicallyfabricated on a single substrate simultaneously. A single substratecould contain thousands or millions of phase change memory elements.

FIGS. 9A and 9B illustrate a plurality of phase change memory elements300 constructed in accordance with a third exemplary embodiment of theinvention. The plurality of phase change memory elements 300 include aphase change material layer 318 formed over sidewalls 320 a of a seconddielectric layer 320. The second dielectric layer 320 is formed over afirst dielectric layer 312 having first electrodes 314 formed over asubstrate 310. A nitride element 316 is formed on the sidewalls 318 a ofthe phase change material layer 318. A second electrode 322 is formedover the nitride element 316 and a third dielectric layer 324 is formedbetween the second electrodes 322.

The FIG. 9A nitride element 316 has first and second surfaces 316 b, 316c, respectively, wherein the length l of the first surface 316 b isshorter than the length l′ of the second surface 316 c; however, it isnot intended to be limiting in any way. For example, the first surface316 b could have a length longer or equal to the length l′ of the secondsurface 316 c.

The phase change memory elements 300 illustrated in FIGS. 9A and 9B areformed in a substantially similar fashion as the phase change memoryelement illustrated in FIGS. 2A and 2B. The second dielectric layer 320,however, is formed prior to the formation of the phase change materiallayer 318 and the nitride element 316. The second dielectric layer isformed over the first dielectric layer 312 and first electrodes 314; thesecond dielectric layer is then selectively etched to create vias 340having sloped sidewalls 320 a. Conformal or partially conformal phasechange material is deposited on the sidewall 320 a and bottom 340 aportions of the vias 340, and selectively etched to create vias 342within the phase change material layer 318. The nitride elements 316 aredeposited within vias 342, and the entire intermediate structure isplanarized. The second electrodes 322 are formed over the phase changematerial layer 318, and within vias selectively etched into the thirddielectric layer 324. Although the vias 342 are illustrated as having arectangular cross-sectional shape, it is not intended to be limiting inany way; for example, the vias 342 could have additional cross-sectionalshapes other than rectangular.

FIGS. 10A and 10B illustrate a plurality of phase change memory elements400 constructed in accordance with a fourth exemplary embodiment of theinvention. The plurality of phase change memory elements 400 include aphase change material layer 418 formed over sidewalls 420 a of a seconddielectric layer 420, which is formed over a first electrode 414. Thefirst electrodes 414 are formed within a first dielectric layer 412,which is formed over a substrate 410. A second electrode 422 is formedover a nitride element 416 formed over the phase change material layer418. A third dielectric layer 424 is formed between the secondelectrodes 422.

The FIG. 10B phase change material layer 418 has a first diameter dcorresponding to the diameter as measured across a surface of the phasechange material layer 418 nearest the first electrode 414. The phasechange material has a second diameter d′ corresponding to the diameteras measured across a surface of the phase change material layer 418nearest the second electrode 422. FIG. 10A illustrates the phase changematerial layer 418 having a planar portion 418 a that is formed over thefirst electrode and two lateral portions 418 b formed over the sidewalls420 a of a second dielectric layer 420. The illustrated phase changematerial layer 418 has a middle portion 418 a that is deposited to coatthe area defined by diameter d and has a top surface 418 a′ that has aheight less than a top surface 418 b′ of the lateral portions 418 b ofthe phase change material layer 418.

The FIG. 10A phase change memory elements 400 are formed by providingthe second dielectric layer 420, and patterning the dielectric layer 420such that several vias are formed. A conformal or substantiallyconformal phase change material is deposited onto the sidewall andbottom regions of the vias to form the phase change material layer 418followed by the deposition of the nitride elements 416. The entireintermediate structure could be planarized, and a third dielectric layer424 is deposited and selectively etched to create vias, wherein secondelectrodes 422 are formed.

FIGS. 11A and 11B illustrate a plurality of phase change memory elements500 constructed in accordance with a fifth exemplary embodiment of theinvention. The plurality of phase change memory elements 500 comprise aphase change material layer 518 formed over sidewalls 520 a of a seconddielectric layer 520 and formed over a first electrode 514. The phasechange memory elements 500 are nearly identical to the phase changememory elements 400 illustrated in FIGS. 10A and 10B; however, sidewalls518 b of the phase change material layer 518 have flared portions 518 c,which increase the surface area of the lateral portion 518 b that is inproximity to a second electrode 522.

FIGS. 11C-11E illustrate an exemplary method of fabricating the phasechange memory element 500 illustrated in FIGS. 11A and 11B. FIG. 11Cillustrates a phase change material layer 518 formed such that the phasechange material layer 518 has sidewalls 518 b, a bottom portion 518 b,and flared portions 518 c (FIG. 11B) formed over a first surface 520 bof the second dielectric layer 520, which collectively form a trench, asillustrated in FIG. 11C. A nitride element 516 is formed within thetrench, such that the nitride element 516 is formed on the sidewalls 518a and the bottom portion 518 a of the phase change material layer 518.

FIG. 11D illustrates the planarization of the nitride element 516 andthe phase change material layer 518, and the deposition of a secondelectrode precursor material layer 522′ formed over the planarizedsurface 526. Once the second electrode precursor 522′ has beendeposited, the FIG. 11D structure is selectively etched to form vias 544to the second dielectric layer 520 illustrated in FIG. 11E. The thirddielectric layer 524 (FIG. 11A) is subsequently deposited over theentire FIG. 11E structure.

The FIG. 11A flared portions 518 c have a cross-sectional width wgreater than the thickness w′ of the sidewalls 518 b. The greater widthw of the flared portions 518 e allows for a greater amount of surfacearea in proximity to the second electrode 522. Therefore, in operation,the current density in the sidewalls 518 b is significantly larger thanthe current density in the flared portions 518 c to ensure only thesidewalls 518 b comprise programmable volume and switches state. Theflared portions 518 c isolate the programmable volume (the sidewalls 518b) from the electrodes 522 to reduce heat loss to the electrode 522,which may further reduce the current necessary to change the state ofsidewalls 518 b.

FIG. 12 illustrates a simplified processor system 900 which includes amemory circuit 901 having a phase change memory elements 100 constructedin accordance with the invention as described above with respect toFIGS. 2A-11B (e.g., phase change memory element 100, 200, 300, 400,500).

The FIG. 12 processor system 900, which can be any system including oneor more processors, for example, a computer system, generally comprisesa central processing unit (CPU) 902, such as a microprocessor, a digitalsignal processor, or other programmable digital logic devices, whichcommunicates with an input/output (I/O) device 906 over a bus 904. Thememory circuit 901 communicates with the CPU 902 over bus 904 typicallythrough a memory controller.

In the case of a computer system, the processor system 900 may includeperipheral devices such as a compact disc (CD) ROM drive 910, which alsocommunicate with CPU 902 and hard drive 905 over the bus 904. Memorycircuit 901 is preferably constructed as an integrated circuit, whichincludes a memory array 903 having at least one phase change memoryelement 100 according to the invention. If desired, the memory circuit901 may be combined with the processor, for example CPU 900, in a singleintegrated circuit.

The above description and drawings are only to be consideredillustrative of exemplary embodiments, which achieve the features andadvantages of the present invention. Modification and substitutions tospecific process conditions and structures can be made without departingfrom the spirit and scope of the present invention. Accordingly, theinvention is not to be considered as being limited by the foregoingdescription and drawings, but is only limited by the scope of theappended claims.

1. A memory element comprising: a substrate supporting a firstelectrode; a dielectric layer over the first electrode having a viaexposing a portion of the first electrode; a phase change material layerformed over sidewalls of the via and contacting the exposed portion ofthe first electrode; insulating material formed over the phase changematerial layer; and a second electrode formed over the insulatingmaterial and contacting the phase change material layer.
 2. The memoryelement of claim 1, wherein the phase change material layer forms atrench within the via, and the insulating material fills the trench. 3.The memory element of claim 2, wherein the phase change material layerhas a middle portion overlying the exposed portion of the firstelectrode, the middle portion of the phase change material layer havinga top surface having a height less than a top surface of lateralportions of the phase change material layer.
 4. The memory element ofclaim 3, wherein the top surface of the middle portion of the phasechange material layer has a smaller diameter than the top surface oflateral portions of the phase change material layer.
 5. The memoryelement of claim 1, wherein the phase change material layer has aU-shaped cross section.
 6. The memory element of claim 1, wherein thephase change material layer is conformal or substantially conformal. 7.The memory element of claim 2, wherein the trench formed by the phasechange material layer extends above a top of the via.
 8. The memoryelement of claim 7, wherein sidewalls of the phase change material layerhave flared portions formed over the top of the via.
 9. The memoryelement of claim 8, wherein the flared portions have a cross-sectionalwidth greater than a thickness of portions of the sidewalls of the phasechange material layer proximate the sidewalls of the via.
 10. The memoryelement of claim 8, wherein the second electrode contacts top surfacesof the flared portions.
 11. A method for manufacturing a memory element,the method comprising: providing a substrate; forming a first electrodeon the substrate; forming a dielectric layer over the first electrode;forming a via in the dielectric layer to expose a portion of the firstelectrode; forming a phase change material layer over sidewalls of thevia such that the phase change material layer contacts the exposedportion of the first electrode; forming insulating material over thephase change material layer; and forming a second electrode over theinsulating material such that the second electrode contacts the phasechange material layer.
 12. The method of claim 11, wherein forming thephase change material layer comprises depositing the phase changematerial on the sidewalls of the via and exposed portion of the firstelectrode to form a trench, and wherein forming the insulating materialcomprises filling the trench with insulating material.
 13. The method ofclaim 12, wherein forming the phase change material layer comprisesforming a middle portion of the phase change material layer overlyingthe exposed portion of the first electrode so as to have a top surfacehaving a height less than a top surface of lateral portions of the phasechange material layer.
 14. The method of claim 13, wherein forming thephase change material layer comprises forming the top surface of themiddle portion of the phase change material layer to have a smallerdiameter than the top surface of lateral portions of the phase changematerial layer.
 15. The method of claim 11, wherein forming the phasechange material layer comprises forming the phase change material layerwith a U-shaped cross section.
 16. The method of claim 11, whereinforming the phase change material layer comprises forming the phasechange material layer to be conformal or substantially conformal. 17.The method of claim 12, wherein forming the trench comprises extendingsidewalls of the phase change material layer above a top of the via. 18.The method of claim 17, further including forming flared portions at atop of the sidewalls of the phase change material layer.
 19. The methodof claim 18, wherein forming the flared portions comprises forming theflared portions so as to have a cross-sectional width greater than athickness of portions of the sidewalls of the phase change materiallayer proximate the sidewalls of the via.
 20. The method of claim 18,wherein forming the second electrode comprises forming the secondelectrode so as to contact top surfaces of the flared portions.